Nanyang Technological University, Singapore (Associated with ERI@N, School of MSE & EEE)
Position- Research Associate Jul’17-Jul'18
Responsibilities:
Nanyang Technological University, Singapore (Associated with ERI@N, School of MSE & EEE)
Position- Graduate Student Researcher Sep’15-May’17
Responsibilities:
CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani (Raj.) India
Sensors and Nanotechnology Group
Position- Project Engineer Mar’14-Jul’15
Responsibilities:
IIT-Bombay and Applied Materials (Dec. 2013)
Completed the CEP certificate course on Semiconductor Technology and Manufacturing.
Greater Noida Institute of Technology (Affiliated with Uttar Pradesh Technical University), Greater Noida, INDIA
B.Tech Major Project: Silicon chip area minimization of BJT & Bipolar IC’s Oct’12-Apr’13
Responsibilities:
Completed the training in DesignKOP Labs, Noida on the project titled “VLSI Design.” (Jul'12-Sep'12)
Guide: Mr. Devendra Khari (Cadence design systems) and Mr. Sanjeev Gupta
Project: Design and implementation of UART on FPGA, Implementation of different gate level modules using Verilog.
National Physical Laboratory, India
Laboratory- Electronics and Instrumentation Cell Jun’12-Jul’12
Position- Undergraduate Research Intern ; Guide- Prof. (Dr.) T.K. Saxena, Chief Scientist
Responsibilities:
Moserbaer, India Jul’11-Aug’11
Summer Internship (Optical Media R&D)
Responsibilities:
Position- Research Associate Jul’17-Jul'18
Responsibilities:
- Micro/ Nano-fabrication in Nanyang Nanofabrication Centre (N2FC) for oxide transistors using flexible & stretchable interconnects and polymeric (pdms, ecoflex) microstructures for wearble sensors (pressure sensor, strain sensor) for healthcare applications
- Photopatterning of self-assembled monolayers, Polymers (PVP, Polystyrene) for AS-ALD based memory applications
Nanyang Technological University, Singapore (Associated with ERI@N, School of MSE & EEE)
Position- Graduate Student Researcher Sep’15-May’17
Responsibilities:
- Used Self-assembled monolayers (OTS, ODTS and DDT) as blocking layers for the inhibition study against ALD precursors for Al2O3 and ZnO, fabrication of capacitors, metal-dielectric patterns
- Fabrication of CNTs, AgNWs, PEDOT:PSS and ITO NP’s based transparent conducting electrodes for pressure sensitive e-skin, flexible heaters, elastomeric actuators and electro-chromic devices
- Worked on transfer printing using thermal release tape and Poly Vinyl Alcohol (PVA) as a sacrificial layer for the transfer of microstructures
CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani (Raj.) India
Sensors and Nanotechnology Group
Position- Project Engineer Mar’14-Jul’15
Responsibilities:
- Microfabrication of SWCNT chemiresistors on silicon & flexible kapton substrate and characterization for temperature, humidity and NH3 gas sensing applications
- Atomic modeling and simulation of Semi-metallic, Semiconducting SWCNTs with and without defect, -COOH group attached, NH3 molecule attached using ATK toolkit
- Developed signal conditioning circuit for NH3 gas sensor
IIT-Bombay and Applied Materials (Dec. 2013)
Completed the CEP certificate course on Semiconductor Technology and Manufacturing.
Greater Noida Institute of Technology (Affiliated with Uttar Pradesh Technical University), Greater Noida, INDIA
B.Tech Major Project: Silicon chip area minimization of BJT & Bipolar IC’s Oct’12-Apr’13
Responsibilities:
- Reduced the area of the emitter by optimizing the fabrication parameters of BJT using MATLAB
- Studied the variation of different mobility models with different parameters while designing BJT. Simulation was performed using Bipole3Basic.
Completed the training in DesignKOP Labs, Noida on the project titled “VLSI Design.” (Jul'12-Sep'12)
Guide: Mr. Devendra Khari (Cadence design systems) and Mr. Sanjeev Gupta
Project: Design and implementation of UART on FPGA, Implementation of different gate level modules using Verilog.
National Physical Laboratory, India
Laboratory- Electronics and Instrumentation Cell Jun’12-Jul’12
Position- Undergraduate Research Intern ; Guide- Prof. (Dr.) T.K. Saxena, Chief Scientist
Responsibilities:
- Theoretical study on quantum phenomenons and SQUID devices (Jan-July'12)
- Design and implementation of analog circuits i.e. Op-amp and 555 timer based circuits
- Realization of 89c51 based BJT transistor binning machine
Moserbaer, India Jul’11-Aug’11
Summer Internship (Optical Media R&D)
Responsibilities:
- Developed virtual instrumentation of Blu Disc testing machine (ODU-1000) for measurement and analysis of jitter and other parameters using Labview